LOW-POWER RF FROND-END DESIGN FOR A LOW-IF RECEIVER USING SILICON ON INSULATOR CMOS TECHNOLOGY

Ertan Zencir, Numan S. Dogan

Department of Electrical Engineering, NCAT

Emerging space communication transceivers require highly integrated, low-power, low-cost, high performance circuitry. Even though the RF front-ends are still being implemented in Bipolar or BiCMOS technologies, CMOS is still the ideal technology for low-cost integration of complex analog and digital functions. Low-IF receivers can be highly integrated and exhibit high performance at the same time. Fully integrated system-on-a-chip CMOS implementations and low-power, high performance receiver architectures are being explored. Low power requirement of the deep space receivers implies the use of a low-IF architecture.

"Low-power, Low-IF SOI (Silicon on insulator) CMOS receiver for deep space applications" project being conducted at A&T in cooperation with NCSU, and JPL aims at the design of a power efficient fully-integrated (analog + digital) UHF (ultra high frequency) low-IF communication receiver intended for space applications using Silicon On Insulator (SOI) semiconductor processing technology. SOI is a fairly new semiconductor process, which did not find widespread use yet. SOI's main advantage for space applications is its being radiation-hard, which means the semiconductor material is not effected by radiations coming from outer space. This project is funded by NASA Glen Research Center.

RF front-end and intermediate frequency blocks (down to the baseband) of the receiver are being investigated and developed at NCAT Department of Electrical Engineering. A standard CMOS version of the RF Frontend (low-noise amplifier and a mixer cascaded) has been developed by using 0.5-mm HP/Agilent AMOS14TB process. Chip occupies an active die area of 2 mm x 2.5 mm and it contains a individual low-noise amplifier working at 435 MHz, an active doubly-balanced Gilbert mixer downconverting the RF signals around 435 MHz to 2 MHz IF, and RF Frontend containing both. Photograph of the manufactured chip is attached.

SOI version of this chip is under development and expected to be fabricated before March 2002. The next step after the SOI RF frontend implementation in the project will be the power efficient circuit design, layout and fabrication of the intermediate frequency blocks that feed the baseband of the receiver being developed by NCSU. This project is expected to be completed by March 2004.

Photograph of the fabricated standard CMOS RF Front-end chip including LNA, mixer, and LNA + mixer